Feedforward amplifier

ABSTRACT

A feedforward amplifier combines an input signal combined by a first error rejection loop with an error component and a first pilot signal detected by a second error detection loop, thereby canceling out the error component and the first pilot signal residual in the input signal.

TECHNICAL FIELD

[0001] The present invention relates to a feedforward amplifier foramplifying a radio frequency signal and the like with suppressing signalerror.

BACKGROUND ART

[0002] A feedforward amplifier that implements low error characteristicby feedforward error compensation is often used in radio frequenciessuch as VHF, UHF and microwave bands as an amplifier that can achievelow error amplification.

[0003] The feedforward error compensation scheme can achieve good errorcompensation principally, and has an advantage of being able toconfigure an amplifier with very low error. However, it has a problem ofdeteriorating its error characteristics because of reduction in theerror compensation amount of a feedforward system caused by variationsin the amplifier characteristics due to ambient temperature or secularchanges.

[0004] To solve the problem, a system is proposed that introduces apilot signal into a loop constituting the feedforward error compensationsystem, and controls the amplifier and loop of the feedforward system bydetecting the pilot signal.

[0005]FIG. 1 is a block diagram showing a configuration of aconventional feedforward amplifier disclosed in Japanese patentapplication laid-open No. 4-70203, for example. In this figure, thereference numeral 1 designates an input terminal of the feedforwardamplifier; 2 designates a pilot signal oscillator for generating a firstpilot signal (frequency f1); 3 designates a combiner for combining aninput signal supplied from the input terminal 1 with the first pilotsignal; 4 designates a feedforward system; 5 designates a pilot signaloscillator for generating a second pilot signal (frequency f2); 6designates an error detection loop for amplifying the input signalsupplied from the combiner 3, and for extracting an error componentinvolved in the amplification of the input signal; and 7 designates anerror rejection loop for canceling out the error component included inthe input signal.

[0006] The reference numeral 8 designates a divider for dividing theinput signal plus the first pilot signal combined by the combiner 3 intotwo paths; 9 designates a vector regulator for electrically regulatingpassing amplitude and phase of the input signal distributed by thedivider 8; 10 designates a combiner for combining the input signalsupplied from the vector regulator 9 with the second pilot signal; 11designates a main amplifier for amplifying the input signal passingthrough the combining by the combiner 10; 12 designates a delay circuitfor delaying the input signal distributed by the divider 8; and 13designates a dividing combiner for dividing the input signal output fromthe main amplifier 11 into two portions, for supplying a first portionof the input signal to a delay circuit 14, and for extracting the errorcomponent produced by the main amplifier 11 by canceling out the inputsignal component of a second portion of the input signal by combiningthe second portion of the input signal with the input signal delayed bythe delay circuit 12.

[0007] The reference numeral 14 designates the delay circuit fordelaying the input signal supplied from the dividing combiner 13; 15designates a divider for distributing the error component extracted bythe dividing combiner 13 to two paths; 16 designates a vector regulatorfor electrically regulating the passing amplitude and phase of the errorcomponent distributed by the divider 15; 17 designates an auxiliaryamplifier for amplifying the error component output from the vectorregulator 16; and 18 designates a combiner for combining the inputsignal delayed by the delay circuit 14 with the error component afterthe amplification, thereby canceling out the error component included inthe input signal.

[0008] The reference numeral 19 designates a pilot signal detector fordetecting the first pilot signal from the output signal of the divider15; 20 designates a control circuit for controlling the vector regulator9 such that the power level (signal level) of the first pilot signaldetected by the pilot signal detector 19 becomes minimum; 21 designatesa divider for distributing the input signal, the error component ofwhich is canceled out by the combiner 18, to two paths; 22 designates apilot signal detector for detecting the second pilot signal from theinput signal distributed by the divider 21; 23 designates a controlcircuit for controlling the vector regulator 16 such that the powerlevel (signal level) of the second pilot signal detected by the pilotsignal detector 22 becomes minimum; 24 designates a bandpass filter(abbreviated to BPF from now on) for eliminating the first pilot signalfrom the input signal distributed by the divider 21; and 25 designatesan output terminal of the feedforward amplifier.

[0009] Next, the operation will be described.

[0010] First, when the combiner 3 combines the input signal suppliedfrom the input terminal 1 with the first pilot signal, the errordetection loop 6 amplifies the input signal, and detects the errorcomponent involved in the amplification of the input signal.

[0011] Specifically, the divider 8 of the error detection loop 6 dividesthe input signal supplied from the combiner 3 to two paths. Then, thevector regulator 9 electrically regulates the passing amplitude andphase of a first portion of the input signal. After that, the combiner10 combines the input signal with the second pilot signal, and the mainamplifier 11 amplifies the input signal passing through the combining bythe combiner 10.

[0012] On the other hand, the delay circuit 12 delays a second portionof the input signal divided by the divider 8 by a predetermined timeperiod, and supplies it to the dividing combiner 13.

[0013] The dividing combiner 13, receiving the input signal amplified bythe main amplifier 11, divides the input signal into two portions, andsupplies the first portion of the input signal to the delay circuit 14.On the other hand, it combines the second portion of the input signalwith the input signal supplied from the delay circuit 12. Thus, itextracts the error component the main amplifier 11 generates bycanceling out the input signal component in the input signal afteramplification.

[0014] Here, the error detection loop 6 performs optimization asfollows.

[0015] Specifically, when the pilot signal detector 19 detects the firstpilot signal from the output signal of the divider 15, the controlcircuit 20 controls the vector regulator 9 such that the power level ofthe first pilot signal becomes minimum, thereby optimizing the errordetection loop 6.

[0016] The error rejection loop 7 cancels out the error component in theinput signal when the error detection loop 6 extracts the errorcomponent from the input signal.

[0017] Specifically, when the vector regulator 16 of the error rejectionloop 7 electrically regulates the passing amplitude and phase of theerror component distributed by divider 15, and then the auxiliaryamplifier 17 amplifies the error component, the combiner 18 combines theamplified error component with the input signal delayed through thedelay circuit 14, thereby canceling out the error component in the inputsignal. Thus, the error component in the input signal is canceled out bycombining the input signal with the error component with the identicalamplitude and opposite phase to those of the error component in theamplified input signal.

[0018] The error rejection loop 7 performs optimization as follows.

[0019] Specifically, when the pilot signal detector 22 detects thesecond pilot signal in the output signal of the divider 21, the controlcircuit 23 controls the vector regulator 16 such that the power level ofthe second pilot signal becomes minimum, thereby optimizing the errorrejection loop 7.

[0020] The BPF 24 rejects the first pilot signal included in one of thetwo portions output from the divider 21 that divides the combined inputsignal fed from the combiner 18 into two paths, and supplies the outputterminal 25 only with the input signal component of the input signal.

[0021] As is clear from the foregoing description, optimizing the errordetection loop 6 and the error rejection loop 7 constituting thefeedforward error compensation system can implement the optimum errorcompensation regardless of the ambient temperature change or secularchange.

[0022] However, the conventional example (referred to as conventionalexample 1 from now on) has the following problems.

[0023] Specifically, according to the conventional example 1, althoughthe second pilot signal used for optimizing the error rejection loop 7can be canceled out principally by the error rejection loop 7 because itis monitored at the output side of the feedforward system 4, the firstpilot signal used for optimizing the error detection loop 6 cannot becanceled out principally because it is not monitored at the output sideof the feedforward system 4 (it is monitored at the divider 15). Forthis reason, the BPF 24 is used for canceling out the first pilotsignal.

[0024] The BPF 24, however, has a large size and high loss in general,thereby presenting a problem of hindering the feedforward amplifier frombeing miniaturized and made highly efficient. More specifically, toachieve precise control of the feedforward amplifier, the frequency ofthe pilot signal must be made as close as possible to the frequency ofthe input signal to be amplified.

[0025] The close frequencies, however, present a problem of increasingthe size and loss of the BPF 24 because the BPF 24 must have such acharacteristic as passing the amplified input signal and rejecting thepilot signal.

[0026] To solve the foregoing problem, a scheme of eliminating the firstpilot signal used for optimizing the error detection loop 6 (it iscalled conventional example 2 from now on). The technique is disclosedin Japanese patent application laid-open No. 4-83407, for example. FIG.2 is a block diagram showing a configuration of a conventionalfeedforward amplifier disclosed in Japanese patent application laid-openNo. 4-83407. In this figure, the same reference numerals designate thesame or like portions to those of FIG. 1, and hence the descriptionthereof is omitted here.

[0027] The reference numeral 26 designates a vector regulator forelectrically regulating the passing amplitude and phase of the firstpilot signal; 27 designates a pilot signal amplifier for amplifying thefirst pilot signal; 28 designates a combiner for combining the firstpilot signal with the input signal divided by the divider 21, therebycanceling out the first pilot signal in the input signal; 29 designatesa divider for dividing the combined input signal supplied from thecombiner 28; 30 designates a pilot signal detector for detecting thefirst pilot signal; and 31 designates a control circuit for controllingthe vector regulator 26 such that the power level (signal level) of thefirst pilot signal detected by the pilot signal detector 30 becomesminimum.

[0028] According to the conventional example 2, when the divider 21divides the input signal and outputs its part, and then the pilot signalamplifier 27 amplifies the first pilot signal as in the conventionalexample 1, the combiner 28 combines the first pilot signal with theinput signal divided by the divider 21, thereby canceling out the firstpilot signal in the input signal. Specifically, the first pilot signalcontained in the input signal is canceled out by the first pilot signalwith the identical amplitude and opposite phase to those of the firstpilot signal in the input signal.

[0029] In this case, to increase the rejection accuracy of the firstpilot signal, when the pilot signal detector 30 detects the first pilotsignal from the output signal of the divider 29, the control circuit 31controls the vector regulator 26 such that the power level of the firstpilot signal becomes minimum.

[0030] The conventional example 2, however, comprises the pilot signalamplifier 27 for canceling out the first pilot signal. The pilot signalamplifier 27 brings about a rather large power consumption, and is usedonly for canceling out the pilot signal, thereby not contributing to theerror compensation of the feedforward amplifier. Thus, although theerror performance of the entire feedforward amplifier is not improved,its efficiency is decreased and its size is increased. In addition, thecombiner 28, which is installed at the output side of the feedforwardamplifier, causes a loss, offering a problem of reducing the efficiencyand increasing the size of the device.

[0031] To avoid the problems involved in using the pilot signal tooptimize the error detection loop 6 in the conventional examples 1 and2, a technique is proposed that controls the vector regulator bydetecting the level of the input signal itself without using the pilotsignal to optimize the error detection loop 6, which is disclosed inJapanese patent application publication No. 7-77330.

[0032] However, when the input signal is not supplied or very small, thecontrol of the error detection loop 6 is impossible. Accordingly, whenthe input signal increases sharply (such as in a burst operation of amobile communication), the loop control lags behind it, therebypresenting a problem of temporarily deteriorating the performance of thefeedforward amplifier.

[0033] With the foregoing configurations, the conventional feedforwardamplifiers have the following problems. The conventional example 1,which comprises the BPF 24 to prevent the first pilot signal from beingoutput from the output terminal 25, has a problem in that since the BPF24 has a large size and high loss in general, it not only increases thesize of the feedforward amplifier, but also reduces the efficiencythereof.

[0034] The conventional example 2, which cancels out the first pilotsignal using the pilot signal amplifier 27 and combiner 28 to obviatethe BPF 24 from its component, has a problem in that since the pilotsignal amplifier 27 and combiner 28 have some power consumption andloss, they increase the size of the feedforward amplifier and reducesthe efficiency thereof without improving the error characteristic of thefeedforward amplifier.

[0035] The method that optimizes the error detection loop by detectingthe level of the input signal itself has a problem of deteriorating theerror characteristic temporarily in the burst operation or the likebecause it cannot perform optimization control when the input signal isnot supplied or very small.

[0036] The present invention is implemented to solve the foregoingproblems. Therefore, an object of the present invention is to provide asmall-size, highly efficient feedforward amplifier capable ofcompensating for the error characteristic.

DISCLOSURE OF THE INVENTION

[0037] According to a first aspect of the present invention, there isprovided a feedforward amplifier that combines the input signal combinedby first error rejection means with an error component and a first pilotsignal detected by second error detection means, thereby canceling outthe error component and the first pilot signal residual in the inputsignal.

[0038] It offers an advantage of being able to compensate for the errorcharacteristic at high efficiency with a small device size.

[0039] The feedforward amplifier in accordance with the presentinvention may adjust the amplitude and phase of the error component andthe first pilot signal detected by the second error detection means tominimize a signal level of the first pilot signal.

[0040] It offers an advantage of being able to minimize the output ofthe first pilot signal.

[0041] The feedforward amplifier in accordance with the presentinvention may adjust the amplitude and phase of the input signalcombined with the first pilot signal by the combining means to minimizea signal level of the first pilot signal.

[0042] It offers an advantage of being able to improve the compensationaccuracy of the error characteristic.

[0043] The feedforward amplifier in accordance with the presentinvention may combine a second pilot signal with the input signal, thefirst error rejection means adjusts amplitude and phase of the errorcomponent and the second pilot signal detected by the first errordetection means to minimize a signal level of the second pilot signal.

[0044] It offers an advantage of being able to improve the compensationaccuracy of the error characteristic.

[0045] The feedforward amplifier in accordance with the presentinvention may adjust the amplitude and phase of the error componentdetected by the first error detection means to minimize a signal levelof the error component.

[0046] It offers an advantage of being able to improve the compensationaccuracy of the error characteristic.

[0047] The feedforward amplifier in accordance with the presentinvention may adjust the amplitude and phase of the input signalsupplied to the combining means to minimize a signal level of an inputsignal component contained in the input signal combined by the firsterror rejection means.

[0048] It offers an advantage of being able to improve the compensationaccuracy of the error characteristic.

[0049] The feedforward amplifier in accordance with the presentinvention may adjust, when the first error detection means combines asecond pilot signal with the input signal, the amplitude and phase ofthe error component and the first and second pilot signals detected bythe second error detection means to minimize a signal level of the firstand second pilot signals.

[0050] It offers an advantage of being able to achieve good errorcompensation over a wide range.

[0051] The feedforward amplifier in accordance with the presentinvention may cause, when the amplitude and phase are controlled by thevector regulators in the first error detection means, in the first errorrejection means and in the second error rejection means, the vectorregulators to be each controlled by common control means.

[0052] It offers an advantage of being able to implement a low cost,small size feedforward amplifier.

[0053] The feedforward amplifier in accordance with the presentinvention may combine the first pilot signal with the input signalcombined by the combining means to cancel out the first pilot signalcontained in the input signal, and detect the error component and thefirst pilot signal by using the input signal in which the first pilotsignal is canceled out.

[0054] It offers an advantage of being able to miniaturize thefeedforward amplifier.

[0055] The feedforward amplifier in accordance with the presentinvention may further comprise in addition to the first and second errordetection means and first and second error rejection means, at least oneerror detection means and at least one error rejection means to increasea number of stages of the error detection means and error rejectionmeans to at least three.

[0056] It offers an advantage of being able to implement moresatisfactory error compensation, thereby achieving a good errorcharacteristic.

BRIEF DESCRIPTION OF THE DRAWINGS

[0057]FIG. 1 is a block diagram showing a configuration of aconventional feedforward amplifier;

[0058]FIG. 2 is a block diagram showing another configuration of aconventional feedforward amplifier;

[0059]FIG. 3 is a block diagram showing a configuration of an embodiment1 of the feedforward amplifier in accordance with the present invention;

[0060]FIG. 4 is a block diagram showing a configuration of an embodiment2 of the feedforward amplifier in accordance with the present invention;

[0061]FIG. 5 is a block diagram showing a configuration of an embodiment3 of the feedforward amplifier in accordance with the present invention;

[0062]FIG. 6 is a block diagram showing a configuration of an embodiment4 of the feedforward amplifier in accordance with the present invention;

[0063]FIG. 7 is a block diagram showing a configuration of an embodiment5 of the feedforward amplifier in accordance with the present invention;

[0064]FIG. 8 is a block diagram showing a configuration of an embodiment6 of the feedforward amplifier in accordance with the present invention;and

[0065]FIG. 9 is a block diagram showing a configuration of an embodiment7 of the feedforward amplifier in accordance with the present invention.

BEST MODE FOR CARRYING OUT THE INVENTION

[0066] The best mode for carrying out the invention will now bedescribed with reference to the accompanying drawings to explain thepresent invention in more detail.

[0067] Embodiment 1

[0068]FIG. 3 is a block diagram showing a configuration of an embodiment1 of the feedforward amplifier in accordance with the present invention.In this figure, the reference numeral 41 designates an input terminal ofa feedforward amplifier; 42 designates a divider for dividing the inputsignal into two paths; 43 designates a pilot signal oscillator forgenerating a first pilot signal (frequency fl); and 44 designates acombiner for combining the first pilot signal with the input signalsupplied from the input terminal 41. The pilot signal oscillator 43 andthe combiner 44 constitute a combining means.

[0069] The reference numeral 45 designates a feedforward system; 46designates a first error detection loop (first error detection means)for amplifying the input signal output from the combiner 44, and fordetecting the error component produced in the amplification of the inputsignal; 47 designates a first error rejection loop (first errorrejection means) for canceling out the error component in the amplifiedinput signal; and 48 designates a pilot signal oscillator for generatinga second pilot signal (frequency f2).

[0070] The reference numeral 49 designates a divider for dividing theinput signal which is combined with the first pilot signal by thecombiner 44 into two paths; 50 designates a vector regulator forelectrically regulating the passing amplitude and phase of the inputsignal divided by the divider 49; 51 designates a combiner for combiningthe second pilot signal with the input signal the vector regulator 50outputs; 52 designates a main amplifier for amplifying the input signaloutput combined by the combiner 51; 53 designates a delay circuit fordelaying the input signal divided by the divider 49; and 54 designates adividing combiner for dividing the input signal amplified by the mainamplifier 52 into two portions, for supplying one of them to a delaycircuit 55, and for combining the other of them with the input signaldelayed through the delay circuit 53, thereby canceling out the inputsignal component of the other input signal to extract the errorcomponent produced by the main amplifier 52.

[0071] The reference numeral 55 designates the delay circuit fordelaying the input signal supplied from the dividing combiner 54; 56designates a divider for dividing the error component extracted by thedividing combiner 54 into two paths; 57 designates a vector regulatorfor electrically regulating the passing amplitude and phase of the errorcomponent output from the divider 56; 58 designates an auxiliaryamplifier for amplifying the error component the vector regulator 57outputs; and 59 designates a combiner for combining the input signaldelayed through the delay circuit 55 with the amplified error componentto cancel out the error component in the input signal.

[0072] The reference numeral 60 designates a pilot signal detector fordetecting the first pilot signal from the output signal of the divider56; 61 designates a control circuit for controlling the vector regulator50 such that the power level (signal level) of the first pilot signaldetected by the pilot signal detector 60 becomes minimum; 62 designatesa divider for dividing the input signal, from which the combiner 59cancels out the error component, into two paths; 63 designates a pilotsignal detector for detecting the second pilot signal from the inputsignal output from the divider 62; and 64 designates a control circuitfor controlling the vector regulator 57 such that the power level(signal level) of the second pilot signal detected by the pilot signaldetector 63 becomes minimum.

[0073] The reference numeral 65 designates a second error detection loop(second error detection means) for detecting the error component and thefirst pilot signal residual in the input signal combined by the firsterror rejection loop 47; and 66 designates a second error rejection loop(second error rejection means) for combining the input signal combinedby the first error rejection loop 47 with the error component and thefirst pilot signal extracted by the second error detection loop 65 tocancel out the error component and the first pilot signal residual inthe input signal.

[0074] The reference numeral 67 designates a delay circuit for delayingthe input signal divided by the divider 42; 68 designates a dividingcombiner for supplying the input signal divided by the divider 62 to adelay circuit 69, and for extracting the error component and the firstpilot signal residual in the input signal by combining the input signaldivided by the divider 62 with the delayed input signal; 69 designatesthe delay circuit for delaying the input signal supplied from thedividing combiner 68; 70 designates a vector regulator for electricallyregulating the passing amplitude and phase of the error component andthe first pilot signal extracted by the dividing combiner 68; 71designates an auxiliary amplifier for amplifying the error component andthe first pilot signal; and 72 designates a combiner for combining theinput signal delayed by the delay circuit 69 with the amplified errorcomponent and first pilot signal, thereby canceling out the errorcomponent and the first pilot signal in the delayed input signal.

[0075] The reference numeral 73 designates a divider for dividing theinput signal, from which the combiner 72 cancels out the error componentand the first pilot signal, into two paths; 74 designates an outputterminal of the feedforward amplifier; 75 designates a pilot signaldetector for detecting the first pilot signal from the output signal ofthe divider 73; and 76 designates a control circuit for controlling thevector regulator 70 such that the power level (signal level) of thefirst pilot signal detected by the pilot signal detector 75 becomesminimum.

[0076] Next, the operation will be described.

[0077] First, the divider 42 divides the input signal supplied from theinput terminal 41 into two paths, and the combiner 44 combines one ofthem with the first pilot signal. Then, the first error detection loop46 amplifies the input signal, and detects the error component involvedin the amplification of the input signal.

[0078] Specifically, when the divider 49 of the first error detectionloop 46 divides the input signal output from the combiner 44 into twopaths, the vector regulator 50 electrically regulates the passingamplitude and phase of a first portion of the input signal.Subsequently, the combiner 51 combines the input signal with the secondpilot signal, and the main amplifier 52 amplifies the input signalcombined by the combiner 51.

[0079] In parallel with this, the delay circuit 53 delays a secondportion of the input signal divided by the divider 49 by a predeterminedtime period, and supplies the input signal to the dividing combiner 54.

[0080] Receiving the amplified input signal from the main amplifier 52,the dividing combiner 54 divides the input signal into two portions, andsupplies a first portion of the input signal to the delay circuit 55.Besides, it combines the second portion of the input signal with theinput signal output from the delay circuit 53, thereby detecting theerror component produced by the main amplifier 52 by canceling out theinput signal component in the amplified input signal.

[0081] Here, the first error detection loop 46 is optimized as follows.

[0082] Specifically, when the pilot signal detector 60 detects the firstpilot signal from the output signal of the divider 56, the controlcircuit 61 controls the vector regulator 50 such that the power level ofthe first pilot signal becomes minimum, thereby optimizing the firsterror detection loop 46.

[0083] When the first error detection loop 46 extracts the errorcomponent in the input signal, the first error rejection loop 47 cancelsout the error component in the input signal.

[0084] Specifically, the vector regulator 57 of the first errorrejection loop 47 electrically regulates the passing amplitude and phaseof the error component output from the divider 56, and the auxiliaryamplifier 58 amplifies the error component. Then the combiner 59combines the amplified error component with the input signal delayedthrough the delay circuit 55, thereby canceling out the error componentin the input signal (canceling out the error component in the inputsignal by combining it with the error component with the identicalamplitude and opposite phase to those of the error component in theamplified input signal).

[0085] Here, the first error rejection loop 47 is optimized as follows.

[0086] Specifically, when the pilot signal detector 63 detects thesecond pilot signal in the output signal of the divider 62, the controlcircuit 64 controls the vector regulator 57 such that the power level ofthe second pilot signal becomes minimum, thereby optimizing the firsterror rejection loop 47.

[0087] The second error detection loop 65 extracts the error componentresidual in the input signal supplied from the first error rejectionloop 47 (although the error component is eliminated by the first errorrejection loop 47, a little error component remains in practice), andthe first pilot signal (the first pilot signal is not canceled outprincipally by the feedforward system 45).

[0088] Specifically, receiving the input signal from the divider 62, thedividing combiner 68 supplies the input signal to the delay circuit 69.In parallel with this, the dividing combiner 68 combines the inputsignal with the input signal delayed by the delay circuit 67 (that is,combines the input signal with the delayed input signal with theidentical amplitude and opposite phase to the input signal divided bythe divider 62), thereby canceling out the input signal component of theinput signal. Thus, the dividing combiner 68 extracts the errorcomponent and the first pilot signal residual in the input signal.

[0089] The second error rejection loop 66 combines the input signalcombined by the first error rejection loop 47 with the error componentand the first pilot signal extracted by the second error detection loop65, thereby canceling out the error component and the first pilot signalresidual in the input signal.

[0090] Specifically, the combiner 72 combines the input signal delayedby the delay circuit 69 with the error component and first pilot signalamplified by the auxiliary amplifier 71 (that is, combines the delayedinput signal with the error component and first pilot signal having theidentical amplitude and opposite phase to the error component and firstpilot signal residual in the delayed input signal), thereby cancelingout the error component and the first pilot signal residual in thedelayed input signal. Thus, the combiner 72 supplies the input signal tothe output terminal 74 through the divider 73.

[0091] In this case, to increase the rejection accuracy of the firstpilot signal, when the pilot signal detector 75 detects the first pilotsignal in the output signal of the divider 73, the control circuit 76controls the vector regulator 70 such that the power level of the firstpilot signal becomes minimum.

[0092] As described above, the present embodiment 1 is configured suchthat it combines the input signal combined by the first error rejectionloop 47 with the error component and the first pilot signal extracted bythe second error detection loop 65, thereby canceling out the errorcomponent and the first pilot signal residual in the input signal. Thus,the present embodiment offers an advantage of being able to compensatefor the error characteristic at high efficiency with compact size.

[0093] Specifically, it can implement a feedforward amplifier at a verylow error rate by canceling out the first pilot signal which is outputfrom the output terminal of the feedforward amplifier of theconventional example 1, and by performing the error compensation onceagain by the feedforward system.

[0094] The first pilot signal is utilized for optimizing the first errordetection loop 46 and the second error rejection loop 66, and the secondpilot signal is utilized for optimizing the first error rejection loop47. Thus, even if the characteristics of the components of thefeedforward system such as amplifiers vary because of the changes in theambient temperature and fluctuations in the supply voltage of thefeedforward amplifier, the error compensation characteristic of thefeedforward system is maintained in a favorable state in its entirety.Thus, a low error rate, highly efficient, small size amplifier can beimplemented.

[0095] Furthermore, since the first error detection loop 46 is alwaysmaintained at the optimum state thanks to the first pilot signal, thefeedforward amplifier can be always maintained at the optimum state evenwithout the input signal, which differs from the conventional examplethat controls the error detection loop without using pilot signal.Therefore, the amplifier characteristic is maintained at the favorablecondition even when the input signal increases sharply (as in the burstoperation).

[0096] Incidentally, the positional relationship can be varied of thevector regulator 50, combiner 51 and main amplifier 52 that constitutethe first error detection loop 46.

[0097] For example, the combiner 51 may be placed at the output side ofthe main amplifier 52, or at an intermediate position between the stageswhen the main amplifier 52 consists of a multi-stage amplifier. Besides,the vector regulator 50 may be inserted into the path of the delaycircuit 53.

[0098] Likewise, the order of the divider 56, vector regulator 57 andauxiliary amplifier 58 may be changed. For example, the divider 56 maybe placed at the output side of the auxiliary amplifier 58. Severalvariations can be implemented with maintaining the positionalrelationships between the error detection loop and error rejection loopand the position at which the pilot signal is applied. The presentinvention is also effective when a modulated signal is used as the pilotsignals.

[0099] Embodiment 2

[0100]FIG. 4 is a block diagram showing a configuration of an embodiment2 of the feedforward amplifier in accordance with the present invention.In this figure, since the same reference numerals designate the same orlike portions to those of FIG. 3, the description thereof is omittedhere.

[0101] The reference numeral 81 designates an error detector fordetecting an error component from the input signal divided by thedivider 62; and 82 designates a control circuit for controlling thevector regulator 57 such that the power level (signal level) of theerror component detected by the error detector 81 becomes minimum.

[0102] Next, the operation will be described.

[0103] Although the foregoing embodiment 1 is configured such that itinjects the second pilot signal into the feedforward system 45, andoptimizes the first error rejection loop 47 by detecting the secondpilot signal, this is not essential. For example, the configuration ispossible in which the error detector 81 detects the error component inthe input signal, and the control circuit 82 controls the vectorregulator 57 such that the power level of the error component becomesminimum.

[0104] Incidentally, the error detector 81 can be supplied not only withthe output signal of the feedforward amplifier, but also with a part ofthe input signal by dividing it at the input terminal 41.

[0105] In addition to the advantages of the foregoing embodiment 1, thepresent embodiment 2 is less affected by the frequency characteristicand can reduce the error at higher accuracy than the configuration usingthe second pilot signal because it carries out such control that reducesthe power of the error component.

[0106] Embodiment 3

[0107]FIG. 5 is a block diagram showing a configuration of an embodiment3 of the feedforward amplifier in accordance with the present invention.In this figure, since the same reference numerals designate the same orlike portions to those of FIG. 3, the description thereof is omittedhere.

[0108] In FIG. 5, the reference numeral 83 designates a divider fordividing the error component and the first and second pilot signalsextracted by the dividing combiner 68; 84 designates a power leveldetector for detecting the power level (signal level) of the outputsignal of the divider 83; 85 designates a control circuit forcontrolling a vector regulator 86 such that the power level detected bythe power level detector 84 becomes minimum; and 86 designates thevector regulator for electrically regulating the passing amplitude andphase of the input signal divided by the divider 42.

[0109] Next, the operation will be described.

[0110] Although the foregoing embodiment 1 does not make any mention ofthe optimization control of the second error detection loop 65, it ispossible. For example, the configuration can be implemented in which thepower level detector 84 detects the power level of the output signal ofthe dividing combiner 68, and the control circuit 85 controls the vectorregulator 86 such that the power level detected by the power leveldetector 84 becomes minimum.

[0111] Specifically, although the path of the auxiliary amplifier 71 inthe second error rejection loop 66 includes an error of the entirefeedforward system 45, which is extracted by the second error detectionloop 65, when the second error detection loop 65 is not in the optimumstate, the input signal component is not completely canceled out,thereby leaving a small amount thereof. The optimum state of the seconderror detection loop 65 is implemented by minimizing the power of theresidual input signal component. Accordingly, the power level detector84 detects the power level of the output signal of the divider 83, andthe control circuit 85 controls the vector regulator 86 in response tothe power level.

[0112] Thus, the second error detection loop 65 is optimized, and hencethe power of the residual input signal component which is not fullycanceled out becomes minimum. As a result, the power consumption of theauxiliary amplifier 71 can be reduced. Therefore, the present embodimentoffers an advantage of being able to increase the efficiency and reducethe size of the feedforward amplifier in its entirety.

[0113] Embodiment 4

[0114]FIG. 6 is a block diagram showing a configuration of an embodiment4 of the feedforward amplifier in accordance with the present invention.In this figure, since the same reference numerals designate the same orlike portions to those of FIG. 3, the description thereof is omittedhere.

[0115] In FIG. 6, the reference numeral 87 designates a pilot signaldetector for detecting the second pilot signal from the output signal ofthe divider 73.

[0116] Next, the operation will be described.

[0117] Although the foregoing embodiment 1 detects the first pilotsignal to perform the optimization control of the second error rejectionloop 66, it is also possible to detect the second pilot signal toperform the optimization control of the second error rejection loop 66.

[0118] Ideally, the second pilot signal is not output from thefeedforward system 45, because it is canceled out by the first errorrejection loop 47. In the actual feedforward amplifier, however, thefirst error rejection loop 47 is not always ideal, and hence the secondpilot signal can be output a little.

[0119] In view of this, the present embodiment 4 is configured such thatthe pilot signal detector 87, which is installed in addition to thepilot signal detector 75 for detecting the first pilot signal, isprovided to detect the second pilot signal so that one of the signalsdetected by the pilot signal detectors is selectively supplied to thecontrol circuit 76.

[0120] Thus, the present embodiment can minimize the signal level notonly of the first pilot signal, but also of the second pilot signal. Asa result, it offers an advantage of being able to implement favorableerror compensation over a wide range.

[0121] Embodiment 5

[0122]FIG. 7 is a block diagram showing a configuration of an embodiment5 of the feedforward amplifier in accordance with the present invention.In this figure, since the same reference numerals designate the same orlike portions to those of FIG. 3, the description thereof is omittedhere.

[0123] In FIG. 7, the reference numeral 88 designates a pilot signaldetector for detecting the first pilot signal in the output signal ofthe divider 56, 62 or 73; and 89 designates a control circuit forcontrolling the vector regulator 50, 57 or 70 such that the powerlevel(signal level) of the first pilot signal detected by the pilotsignal detector 88 becomes minimum.

[0124] Next, the operation will be described.

[0125] The present embodiment differs from the foregoing embodiment 1 inthat it obviates the pilot signal oscillator 48 for generating thesecond pilot signal, switches the output of the pilot signal oscillator43 for generating the first pilot signal, and supplies it to thecombiner 44 or 51

[0126] In addition, the present embodiment is configured such that thesignal divided by the divider 56, 62 or 73 is detected by the singlepilot signal detector 88 by switching them, and that the control circuit89 controls the vector regulator 50, 57 or 70 such that the signal levelof the corresponding pilot signal becomes minimum.

[0127] When the pilot signal oscillator 43 is connected to the combiner51, the pilot signal detector 88 detects the output signal of thedivider 62, and the control circuit 89 controls the vector regulator 57such that the signal level of the output signal becomes minimum.

[0128] When the pilot signal oscillator 43 is connected to the combiner44, the pilot signal detector 88 detects the output signal of thedivider 56, and the control circuit 89 controls the vector regulator 50such that the signal level of the output signal becomes minimum.Alternatively, it detects the output signal of the divider 73, and thecontrol circuit 89 controls the vector regulator 70 such that the signallevel of the output signal becomes minimum.

[0129] Incidentally, such a configuration is also possible in which onlyone of the pilot signal oscillator 43 the pilot signal detector 88 ismade single, and the other of them is left multiple as in the foregoingembodiment 1.

[0130] With the foregoing configuration, the present embodiment canreduce the number of the pilot signal oscillators and pilot signaldetectors, thereby offering an advantage of being able to reduce thecost and size of the feedforward amplifier.

[0131] Embodiment 6

[0132]FIG. 8 is a block diagram showing a configuration of an embodiment6 of the feedforward amplifier in accordance with the present invention.In this figure, since the same reference numerals designate the same orlike portions to those of FIG. 3, the description thereof is omittedhere.

[0133] In FIG. 8, the reference numeral 90 designates a divider fordividing the input signal delayed by the delay circuit 53; 91 designatesa vector regulator for electrically regulating the passing amplitude andphase of the first pilot signal; 92 designates a combiner for combiningthe first pilot signal with the input signal divided by the divider 90,thereby canceling out the first pilot signal in the input signal; 93designates a divider for dividing the input signal combined by thecombiner 92; 94 designates a pilot signal detector for detecting thefirst pilot signal in the input signal divided by the divider 93; and 95designates a control circuit for controlling the vector regulator 91such that the power level (signal level) of the first pilot signaldetected by the pilot signal detector 94 becomes minimum.

[0134] Next, the operation will be described.

[0135] Although the foregoing embodiment 1 comprises the delay circuit67 for supplying the delayed input signal to the dividing combiner 68,the delay circuit 67 can be eliminated by configuring as shown in FIG.8.

[0136] Specifically, the divider 90 divides the delayed input signaloutput from the delay circuit 53, and the combiner 92 combines the inputsignal divided by the divider 90 with the first pilot signal, therebycanceling out the first pilot signal in the input signal (canceling outthe first pilot signal in the input signal by combining the input signalwith the first pilot signal having the identical amplitude and oppositephase to those of the first pilot signal in the input signal).

[0137] In this case, to increase the rejection accuracy of the firstpilot signal, while the pilot signal detector 94 detects the first pilotsignal in the output signal of the divider 93, the control circuit 95controls the vector regulator 91 such that the power level of the firstpilot signal becomes minimum.

[0138] In this way, the signal appearing at the output of the divider 93includes a slightest part of the first pilot signal, leaving only theinput signal component input to the feedforward amplifier. This signalis supplied to the dividing combiner 68 to be combined with the outputsignal of the feedforward system 45 in the same amplitude and oppositephases, to be used for detecting the error by canceling out the inputsignal component of the feedforward system 45.

[0139] With such a configuration, the present embodiment can obviate thedelay circuit 67 which is necessary in the foregoing embodiment 1. Thus,in addition to the advantages of the foregoing embodiment 1, the presentembodiment offers an advantage of being able to reduce the size of thefeedforward amplifier.

[0140] Embodiment 7

[0141]FIG. 9 is a block diagram showing a configuration of an embodiment7 of the feedforward amplifier in accordance with the present invention.In this figure, since the same reference numerals designate the same orlike portions to those of FIG. 3, the description thereof is omittedhere.

[0142] In FIG. 9, the reference numeral 101 designates a third errordetection loop; 102 designates a third error rejection loop; 103designates a divider for dividing the input signal; 104 designates apilot signal oscillator for generating a third pilot signal (frequencyf3); 105 designates a combiner for combining the third pilot signal withthe input signal; 106 designates a vector regulator for electricallyregulating the passing amplitude and phase of the input signal; 107designates a divider; 108 designates a pilot signal detector fordetecting the third pilot signal; and 109 designates a control circuitfor controlling the vector regulator 106 such that the power level(signal level) of the third pilot signal detected by the pilot signaldetector 108 becomes minimum.

[0143] The reference numeral 110 designates a delay circuit for delayingthe input signal; 111 designates a dividing combiner for supplying theinput signal divided by the divider 73 to a delay circuit 112, and forcombining the input signal divided by the divider 73 with the inputsignal delayed by the delay circuit 110, thereby extracting the errorcomponent and third pilot signal residual in the input signal; 112designates the delay circuit for delaying the input signal supplied fromthe dividing combiner 111; 113 designates a vector regulator forelectrically regulating the passing amplitude and phase of the errorcomponent and third pilot signal extracted by the dividing combiner 111;114 designates an auxiliary amplifier for amplifying the error componentand the third pilot signal; and 115 designates a combiner for combiningthe input signal delayed by the delay circuit 112 with the amplifiederror component and third pilot signal, thereby canceling out the errorcomponent and third pilot signal in the delayed input signal.

[0144] The reference numeral 116 designates a divider for dividing theinput signal, in which the combiner 115 cancels out the error componentand the third pilot signal, into two paths; 117 designates a pilotsignal detector for detecting the third pilot signal in the outputsignal of the divider 116; and 118 designates a control circuit forcontrolling the vector regulator 113 such that the power level (signallevel) of the third pilot signal detected by the pilot signal detector117 becomes minimum.

[0145] Next, the operation will be described.

[0146] Although the error detection loops and the error rejection loopshave the two stage configuration in the foregoing embodiment 1, they canhave a three stage configuration as shown in FIG. 9 by adding the thirderror detection loop 101 and third error rejection loop 102 to the firstand second error detection loops and the first and second errorrejection loops.

[0147] With such a configuration, the present embodiment can furtherreduce the effect of the temperature changes and supply voltagefluctuations because of the increasing number of times of the errorcompensation by the feedforward. Thus, it can implement better errorcompensation, thereby offering an advantage of being able to achieve thebetter error characteristic.

[0148] Incidentally, although the present embodiment 7 shows the threestage configuration of the error detection loops and the error rejectionloops, this is not essential. For example, it is obvious that the fouror more stage configuration can be implemented.

[0149] Furthermore, the foregoing embodiments 2-6 can be combined tocreate new configurations.

[0150] Industrial Applicability

[0151] As described above, the feedforward amplifier in accordance withthe present invention has a small size and high efficiency, and issuitable for compensating for the error characteristic.

What is claimed is:
 1. A feedforward amplifier comprising: combiningmeans for combining an input signal with a first pilot signal; firsterror detection means for amplifying the input signal that is combinedwith the first pilot signal by said combining means, and for detectingan error component in the input signal amplified; first error rejectionmeans for canceling out the error component in the input signalamplified by said first error detection means by combining the inputsignal with the error component; second error detection means fordetecting the error component and the first pilot signal residual in theinput signal combined by said first error rejection means; and seconderror rejection means for combining the input signal combined by saidfirst error rejection means with the error component and the first pilotsignal detected by said second error detection means to cancel out theerror component and the first pilot signal residual in the input signal.2. The feedforward amplifier according to claim 1, wherein said seconderror rejection means adjusts amplitude and phase of the error componentand the first pilot signal detected by said second error detection meansto minimize a signal level of the first pilot signal.
 3. The feedforwardamplifier according to claim 1, wherein said first error detection meansadjusts amplitude and phase of the input signal combined with the firstpilot signal by said combining means to minimize a signal level of thefirst pilot signal.
 4. The feedforward amplifier according to claim 1,wherein when said first error detection means combines a second pilotsignal with the input signal, said first error rejection means adjustsamplitude and phase of the error component and the second pilot signaldetected by said first error detection means to minimize a signal levelof the second pilot signal.
 5. The feedforward amplifier according toclaim 1, wherein said first error rejection means adjusts amplitude andphase of the error component detected by said first error detectionmeans to minimize a signal level of the error component.
 6. Thefeedforward amplifier according to claim 1, wherein said second errordetection means adjusts amplitude and phase of the input signal suppliedto said combining means to minimize a signal level of an input signalcomponent contained in the input signal combined by said first errorrejection means.
 7. The feedforward amplifier according to claim 4,wherein when said first error detection means combines a second pilotsignal with the input signal, said second error rejection means adjustsamplitude and phase of the error component and the first and secondpilot signals detected by said second error detection means to minimizea signal level of the first and second pilot signals.
 8. The feedforwardamplifier according to claim 1, wherein when the amplitude and phase arecontrolled by the vector regulators in said first error detection means,said first error rejection means and said second error rejection means,the vector regulators are each controlled by common control means. 9.The feedforward amplifier according to claim 1, wherein said seconderror detection means combines the first pilot signal with the inputsignal combined by said combining means to cancel out the first pilotsignal contained in the input signal, and detects the error componentand the first pilot signal using the input signal in which the firstpilot signal is canceled out.
 10. The feedforward amplifier according toclaim 1, further comprising in addition to said first and second errordetection means and first and second error rejection means, at least oneerror detection means and at least one error rejection means to increasea number of stages of said error detection means and error rejectionmeans to at least three.